Filter Implementation On Synthup

Jean-Michel Raczinski; Stéphane Sladek; Luc Chevalier
DAFx-1999 - Trondheim
This paper presents different implementations of digital filters on SYNTHUP, a PCI plug-in board based on FPGAs (Field Programmable Gate Arrays). The modular architecture of the board features a PCI interface, seven identical cells dedicated to computing, five FPGAs dedicated to data exchange, one cell for control and a total of 128M bytes of dual port SDRAM. The PCI interface offers bus mastering (scatter-gather DMA) for high speed data transfer between the board and the host memory. Applications are downloaded from the host via PCI into the logical resources of the FPGAs in few milliseconds. Each cell is made up of a FPGA that drives two independent 4M×16 SDRAM. It is connected to a 32 bit control bus and to an array of exchange FPGAs through a 64 bit bus. These FPGAs work as a crossbar switch. Moreover, they drive five 12 bit ports intended for communication with other boards. The paper concentrates on the implementation of FIR serial filters with distributed arithmetic which allows one FPGA to drive 48 channels in real time (48 kHz sampling rate, 16 bit data and coefficients). As the coefficients can be changed, each channel has its own filter (100 taps, adaptive filter). One can also build a 4800 taps filter for one channel.